Reference is made to FIG. 1 which illustrates a basic circuit diagram for a crystal oscillator circuit 10. A crystal resonator 12 is connected between the input and the output of an inverter 14 formed by two complementary transistors (not shown, but understood by those skilled in the art). The output of the oscillator (oscillator output signal OUT) is taken, for example, at the output of the inverter 14. The common mode of the inverter 14 is fixed by a resistor 16 connected between the input and output of the inverter. A frequency correction network comprising two capacitors 18 and 20, respectively connecting the resonator terminals to a reference voltage (such as a ground reference node), enables adjustment of the frequency of oscillator operation.
Reference is made to FIG. 2 which illustrates a circuit diagram of a crystal oscillator circuit 30 with a configuration similar to that of FIG. 1. Here, the oscillator circuit 30 differs from the oscillator circuit 10 (FIG. 1) in that the inverter 14′ has a different configuration. The inverter 14′ comprises an n-channel MOSFET transistor 32 having a source terminal coupled to the ground reference node, a gate terminal coupled to one side of the crystal resonator 12 and a drain terminal coupled to the other side of the crystal resonator. A current source 34 is coupled between a positive supply node (for example, Vdd) and the drain terminal of transistor 32 so as to source current into the drain terminal of transistor 32. The current sourced by current source 34, referred to as the oscillator supply current Isupp, has a magnitude preferably set at the minimum value necessary to maintain oscillation in steady state.
Those skilled in the art understand that the minimum supply current Isupp needed for oscillation is insufficient to achieve a fast start-up of the oscillator circuit 30. Thus, it is known in the art to have current source 34 operate in a variable current mode wherein a relatively higher magnitude current for Isupp is provided at start-up. After oscillation has commenced, the current source switches to source a relatively lower magnitude current, for example the minimum current for oscillator in steady state, for Isupp. The change in current magnitude for Isupp may occur after a predetermined time or after the circuit senses that steady state operation has been reached.
The current source 34 may accordingly comprise a p-channel MOSFET device having its source terminal coupled to the positive supply node, its drain terminal coupled to the drain terminal of the transistor 32 and its gate terminal coupled to receive a variable bias voltage having a magnitude dependent on operating mode, for example, start-up versus steady state operation. See, for example, United States Patent Application Publication No. 2011/0148533 (the disclosure of which is incorporated by reference).
Reference is made to FIG. 3 which illustrates a circuit diagram of a crystal oscillator circuit 40 with a configuration similar to that of FIG. 2. The oscillator circuit 40 is configured with an amplitude limiting circuit 42. The amplitude limiting circuit 42 is coupled through a capacitor 44 to sense the output voltage of the oscillator output signal (OUT). The sensed output voltage is added to a first reference voltage Vref1 supplied through a resistor 46. The resistor 46 and capacitor 44 function as a high pass filter circuit with respect to the oscillator output signal to ensure that the voltage measurement is not perturbed by a DC offset. The peak voltage value of the sensed output voltage is determined by a peak detector circuit 48 and output as the signal Vpeak (the magnitude of this voltage being stored on a capacitor 52). A differential amplifier 50 functions to compare the Vpeak voltage to a second reference voltage Vref2. The differential amplifier 50 functions as an error amplifier in a negative feedback mode. The output Verr from the differential amplifier represents the difference between the Vpeak voltage and second reference voltage Vref2. The voltage Verr is used to bias the gate terminal of a p-channel MOSFET transistor 34′ which functions as a variable current source supplying the oscillator supply current Isupp for operation of the oscillator circuit 30. If the Vpeak voltage exceeds the Vref2 voltage, the bias signal Verr increases causing the transistor 34′ to source less current to the oscillator 30 resulting in a decrease in the voltage of the oscillating output signal OUT. On the contrary, where Vpeak voltage is less than the Vref2 voltage, the bias signal Verr decreases causing the transistor 34′ to source more current to the oscillator 30 resulting in an increase in the voltage of the oscillating output signal OUT. Assuming that the loop gain is sufficient, the amplitude limiting circuit 42 will cause the peak voltage of the oscillating output signal to equal the voltage Vref2−Vref1.
Amplitude limiting circuits like that of FIG. 3 are important because they serve to reduce current consumption of the crystal oscillator 30 to a maximum value equal to that needed to ensure oscillator operation. This is critical in power sensitive applications where the oscillating output signal is always on for supply to on-chip circuitry such as a microprocessor or other digital logic.
Amplitude limiting circuits like that of FIG. 3 are also important because they serve to reduce the drive level of the oscillator crystal, which is proportional to the square of amplitude, and thus reduce aging of the crystal resonator 12.
Amplitude limiting circuits like that of FIG. 3 are still further important because they serve to address and eliminate non-linearity in the oscillating output signal as distortion can be introduced at large signal amplitudes.
There are, however, known drawbacks with respect to the use of circuits like that shown in FIG. 3. One known drawback concerns the need for large resistance and capacitance values for the resistor 46 and capacitors 44 and 52. When the oscillator circuit 40 (with the exception of the crystal 12) is implemented as an integrated circuit, the resistor 46 and capacitors 44 and 52 occupy large amounts of real estate on the die. The circuitry required for implementation of the peak detector circuit 48 can also occupy significant amounts of real estate.
An additional known drawback with respect to certain prior art amplitude limiting circuits is that the current sourced at start-up is not controlled. See, Vittoz, “CMOS Analog Integrated Circuits Based on Weak Inversion Current,” IEEE Journal of Solid-State Circuits, vol. SC-12, no. 3, June 1977 (the disclosure of which is incorporated by reference). It is accordingly difficult to ensure that the transistor transconductance lies above a desired range across all process, voltage and temperature (PVT) corners.
Yet another known drawback with respect to certain prior art amplitude limiting circuits is that operation of the circuit is process and temperature dependent. Variation in the regulated value of peak voltage for the oscillator output signal may occur as a function as process and temperature.
There is accordingly a need in the art for an amplitude limiting circuit, for use for example in connection with a crystal oscillator, which is suitable for implementation as an integrated circuit occupying a minimal amount of die real estate. The circuit should also be relatively insensitive to variation in process and temperature.